1. Field of the Invention
This invention relates to an integrated circuit logic gate compatible with a four-phase, major-minor clocking arrangement and a six-phase metal oxide semiconductor (MOS) system.
2. Prior Art
Integrated circuit field effect transistor (FET) logic circuits, which are strobed by a four-phase, major-minor clocking scheme, can be arranged to form six basic logic gates. Reference may be made to U.S. Ser. No. 659,057, filed Feb. 18, 1976, for a brief description of these aforementioned six basic logic gates.
A first logic gate, commonly designated as a type 2 logic gate (which precharges when multi-phase clock signal .phi..sub.1 comes true and discharges or evaluates when multiphase clock signal .phi..sub.2 comes true) and a second logic gate, commonly designated as a type 4 logic gate (which precharges during .phi..sub.3 and evaluates during .phi..sub.4) are referred to as major gates by those skilled in the art, inasmuch as each gate evaluates during major clock phases .phi..sub.2 and .phi..sub.4, respectively. For a more detailed description of the major logic gate types 2 and 4, reference may be made to U.S. Pat. No. 3,601,627 issued Aug. 24, 1971. However, none of the six basic logic gates is implemented so that both of the major gate types, 2 and 4, can be directly fanned-in without the addition of space consuming interface gates, such as inverters and the like. This is because no single logic gate is known which is adapted to accept information signals when the output of both type 2 and 4 logic gates are good (i.e. the output terminals are isolated from the output terminals thereof).
One example of a MOSFET dynamic logic system including six clock phase inputs is U.S. Pat. No. 3,747,064 issued July 17, 1973.